Orange Pi 3 LTS · 2G8G · Allwinner H6 · bench reference

Orange Pi 3 LTS the 2G/8G board, end to end

A quad-core Cortex-A53 at 1.8 GHz on Allwinner's H6, with 2 GB of LPDDR3, 8 GB of onboard eMMC and real gigabit Ethernet — roughly Raspberry Pi 3B+ compute with two advantages the Pi of that era never had: a network port that isn't hanging off USB, and storage that isn't a microSD card waiting to corrupt. The catch is software, not silicon. Almost everything surprising about this board comes from three facts: the header is 26 pins, not 40, the GPIO banks are split across two different gpiochips that number pins differently depending on which tool you use, and the vendor's own OS images are old enough that the community images are the real answer.

SoC Allwinner H6 · 4× Cortex-A53 @ 1.8 GHz GPU Mali-T720 · GLES 3.1 RAM 2 GB LPDDR3 storage 8 GB eMMC + microSD net YT8531C GbE · AW859A Wi-Fi 5 · BT 5.0 header 26 pins · 17 GPIO power 5 V / 3 A USB-C size 85 × 56 mm · 45 g
Fig. 1 — Orange Pi 3 LTS · board layout, top view H6 Cortex-A53 ×4 LPDDR3 2 GB eMMC 8 GB AW859A Wi-Fi 5 · BT 5.0 AXP805 PMIC YT8531C GbE PHY USB 3.0 host the only 5 Gbit port Gigabit Ethernet YT8531C PHY — not USB-bottlenecked USB 2.0 host u.FL antenna Wi-Fi will not reach without the whip fitted 3.5 mm AV audio out + CVBS video HDMI 2.0a 4K, and the only display output that matters Debug UART GND · RX · TX — 115200 8N1 Power button SW4 USB-C — power in 5 V / 3 A. Also the OTG and FEL recovery port 26-pin GPIO header Not 40 pins. No Pi HAT will fit this board. microSD — underside the slot is on the back of the PCB, right edge 85 mm × 56 mm · 45 g · top view, schematic
Schematic, not to scale. Ports and chip placement follow the vendor's own top-view photograph of the v1.2 board. The microSD slot is the one thing you cannot see from this side — it is on the underside, right-hand edge.

01 · The Board

What is physically on the 85 × 56 mm card, and how it compares to the Pi it is usually cross-shopped against.

What you have

2G8G
SoCAllwinner H6 (V200) — 4× Cortex-A53 @ 1.8 GHz, 64-bit
GPUMali-T720 MP2 — OpenGL ES 3.1 / 3.0 / 2.0 / 1.1
RAM2 GB LPDDR3, shared with the GPU
Storage8 GB eMMC on board + microSD (underside)
VideoHDMI 2.0a (4K) + CVBS composite on the AV jack
AudioHDMI, and analogue on the 3.5 mm jack
Ethernet10/100/1000 via YT8531C PHY
WirelessAW859A — 802.11 a/b/g/n/ac + BT 5.0
USB1× USB 3.0 host, 1× USB 2.0 host, 1× USB 2.0 OTG
Header26 pins — 1× I2C, 1× SPI, 1× UART, 1× PWM, 17 GPIO
Power5 V / 3 A over USB-C, AXP805 PMIC
ExtrasIR receiver, power button (SW4), power + status LEDs

Board dimensions 85 × 56 mm, 45 g. Serials are stamped YYYYMMDD… — the leading eight digits are the manufacture date.

Where everything is

port geography
Left edgeUSB 3.0 (top) · gigabit Ethernet (middle) · USB 2.0 (bottom)
Top edge3.5 mm AV · IR dome · HDMI · 3-pin debug UART · power button
Right edgeUSB-C — power in, and the OTG/FEL port
Bottom edge26-pin header (right) · u.FL antenna socket (centre)
UndersidemicroSD slot, right-hand edge

easy to missThe antenna is a separate whip on a u.FL pigtail. Without it fitted, Wi-Fi range is measured in centimetres. Check it is clipped down before blaming the driver.

Against a Raspberry Pi

honest comparison

Where it wins

Gigabita real RGMII PHY, not Ethernet-over-USB like the Pi 3B+
eMMC8 GB soldered — boots with no card at all, and nothing to corrupt
USB 3.0native to the SoC
Pricesubstantially cheaper for the same rough compute

Where it loses

Softwarethe whole story. Vendor images age badly; mainline support arrived late and piecemeal
26 pinsno Raspberry Pi HAT will fit, mechanically or electrically
Wi-Fi driverout-of-tree — see §02
Communityorders of magnitude smaller; fewer answers when stuck

Pick this board for a wired, headless, always-on job — a service host, a collector, a light container box. Pick a Pi when you need HATs, camera stacks, or the ability to search your way out of trouble.

The 2 GB reality

what fits

2 GB is shared with the Mali GPU, so a framebuffer comes out of your budget. Headless is the sane default and costs you nothing here.

Headless servercomfortable — Pi-hole, MQTT, NAS front-end, print server, reverse proxy
Docker / k3sa few small containers, fine. A stack, no
Desktoppossible, unpleasant. Budget ~600–700 MB before you open anything
Compilinguse -j2 and a swap file, or you will meet the OOM killer
4K videohardware decode only, and only with a vendor kernel that exposes it

The 8 GB eMMC is the tighter constraint in practice. A desktop image plus updates will fill it; keep /var/log in check and put bulk data on USB.

02 · The Silicon

Five chips decide what this board can and cannot do, and three of them explain every driver problem you will hit.

Allwinner H6 · V200

the SoC

A 2017-generation set-top-box part, and the first Allwinner SoC to carry gigabit Ethernet, USB 3.0 and PCIe together. That STB heritage shows: the video path is excellent, the peripheral story is uneven.

CPU4× Cortex-A53 @ 1.8 GHz, ARMv8-A, 64-bit
GPUMali-T720 MP2 — GLES 3.1, no Vulkan
DecodeH.265 to 6K @ 30, H.264 4K @ 30, 4K HDR with Allwinner's Smart Color Engine
EncodeH.264 4K @ 30
MemoryDDR3 / LPDDR3
BootBROM order: microSD → eMMC → SPI NOR → FEL over USB OTG

The datasheet and user manual are public — linux-sunxi hosts the H6 V200 documents, which is unusual for Allwinner and makes this SoC far more tractable than its siblings.

The H6 PCIe problem

why nobody uses it

The H6 has a PCIe 2.0 controller that does not map PCIe address space properly — only 64 KB is reachable at a time, so every access to config, I/O or memory space has to be wrapped by software.

Mainline Linux does not wrap PCIe memory access, and will not, so a correct mainline PCIe driver for the H6 is not possible. Vendor BSP kernels patch the driver to do the wrapping; out-of-tree projects have gone as far as running an EL2 hypervisor shim to trap the accesses.

good newsOn this board it does not matter: the 3 LTS exposes no mini-PCIe or M.2 slot, and the USB 3.0 port is native to the SoC rather than hanging off PCIe. The quirk only bites if you go looking for it.

AW859A · the Wi-Fi trap

read this one

The radio module is labelled AW859A, and the instinct is to assume it is another Ampak/Broadcom part. It is not. Inside is a Unisoc UWE5622 (sc2355). On the earlier Orange Pi 3 this socket held an Ampak AP6256; the LTS swapped it.

consequenceThe UWE5622 has no mainline driver. Wi-Fi and Bluetooth work only with the out-of-tree uwe5622 driver from Allwinner's BSP tree. A generic arm64 distro, a stock mainline kernel, or an OpenWrt build without that module will boot fine and show no wireless interface at all.

is the driver even loaded?lsmod | grep -i uwe · dmesg | grep -i sprd did the interface appear?ip link — no wlan0 means driver, not antenna

This is the single biggest reason to stay on an image built for the board rather than a generic one. Ethernet will always work; Wi-Fi is the canary.

YT8531C

Ethernet PHY

A Motorcomm YT8531C gigabit PHY on RGMII — the same part Orange Pi used on the 4 LTS and the 800. PHY ID 0x4f51e91b.

Mainlinethe motorcomm driver covers YT8531 from kernel 6.3 onward
Before 6.3needs an out-of-tree patch — this is why old generic images have no Ethernet
Tuningthe DT node takes rx-internal-delay-ps and tx-internal-delay-ps; wrong RGMII delays give you a link that negotiates but drops packets

Mainline device-tree support for the Orange Pi 3 LTS specifically only landed in 2025 — this board was a vendor-kernel-only proposition for most of its life.

AXP805

PMIC

An X-Powers AXP805 handles every rail, the power button and the soft power states — the standard companion for an H6.

this explains the headerThe PMIC talks to the SoC over R_I2C, which is PL0 and PL1. That is why the PL bank appears on the 26-pin header with a hole in it: PL0 and PL1 are spoken for, and only PL2, PL3, PL8 and PL10 are brought out.

It is also why the board has a real power button rather than a barrel-jack yank, and why a clean poweroff genuinely powers down instead of halting at a prompt.

Do not probe or drive PL0/PL1 even if you find pads for them — you are on the PMIC's bus.

The supporting cast

everything else
eMMC8 GB, soldered near the top edge. Ships with Android 9 already flashed
LPDDR32 GB, beside the SoC, shared with the GPU
VS838IR receiver — the dome next to the AV jack. Works with the Orange Pi remote
u.FL socketantenna feed at the bottom edge, centre
SW4power button, top-right corner

Reading the chip markings on your own board is worth doing once: the H6 is the large square part in the middle marked ALLWINNER H6 V200-AI, the AW859A is the shielded module below it, the AXP805 is on the right near the USB-C, and the YT8531C sits by the Ethernet jack.

Why the passives are so tiny

0402 and 0201

Squint at the silkscreen and you will find hundreds of parts — R1234, C120, CC51 — most of them 0402 (1.0 × 0.5 mm) with a scattering of 0201 (0.6 × 0.3 mm). That is not showing off. Four things force it:

Areaa BGA SoC, DRAM, eMMC, PMIC, PHY, radio module, four USB, HDMI and RJ45 on 85 × 56 mm. Every rail needs decoupling; there is nowhere else to put it
Inductancethe real reason. A capacitor's parasitic ESL scales with package size — an 0805 is electrically useless as a high-frequency decoupler. Small is not a compromise, it is the requirement
Proximitydecoupling has to sit at the ball. 0402s fit between the vias of a BGA escape pattern; larger parts do not
Assemblypick-and-place handles 0402 all day, reels are cheap, and no human was ever going to place these

for rework0402 is hand-solderable with a fine tip, good flux and tweezers. 0201 effectively is not — that is hot-air or a microscope. Before you attempt it, note that many of these are DDR3 or RGMII terminations where the value and position matter to signal integrity, so a "close enough" replacement can give you a board that boots and then corrupts memory.

Fig. 2 — the 26-pin GPIO header, looking down at the board odd pins · board edge even pins · inner row 1 3.3V OUT 2 5V OUT 3 PD26 I2C0 SDA gpiochip1 line 122 wiringOP 122 4 5V OUT 5 PD25 I2C0 SCK gpiochip1 line 121 wiringOP 121 6 GND 7 PD22 PWM0 gpiochip1 line 118 wiringOP 118 8 PL2 gpiochip0 line 2 wiringOP 354 9 GND 10 PL3 gpiochip0 line 3 wiringOP 355 11 PD24 UART3 RX gpiochip1 line 120 wiringOP 120 12 PD18 gpiochip1 line 114 wiringOP 114 13 PD23 UART3 TX gpiochip1 line 119 wiringOP 119 14 GND 15 PL10 gpiochip0 line 10 wiringOP 362 16 PD15 gpiochip1 line 111 wiringOP 111 17 3.3V OUT 18 PD16 gpiochip1 line 112 wiringOP 112 19 PH5 SPI1 MOSI gpiochip1 line 229 wiringOP 229 20 GND 21 PH6 SPI1 MISO gpiochip1 line 230 wiringOP 230 22 PD21 gpiochip1 line 117 wiringOP 117 23 PH4 SPI1 CLK gpiochip1 line 228 wiringOP 228 24 PH3 SPI1 CS gpiochip1 line 227 wiringOP 227 25 GND 26 PL8 gpiochip0 line 8 wiringOP 360 3.3 V 5 V GND GPIO I2C0 SPI1 UART3 PWM0
Pin 1 is the corner nearest the board edge. Odd pins run down the outer row, even pins down the inner row — the same convention as a Raspberry Pi, on a header that is otherwise nothing like one. Port names and functions are the vendor's; the gpiochip line numbers are what libgpiod wants, and the wiringOP numbers are what gpio readall prints. They are not the same for the PL bank.

What is actually on it

17 GPIO

Twenty-six pins: 9 power and ground, 17 usable GPIO. The vendor's own summary is "1× I2C, 1× SPI, 1× UART & multiple GPIO" — and that is the whole story, plus one PWM.

BusPinsNode
I2C03 SDA · 5 SCK/dev/i2c-0
SPI119 MOSI · 21 MISO · 23 CLK · 24 CS/dev/spidev1.0
UART311 RX · 13 TX/dev/ttyS3
PWM07sysfs pwmchip

Everything else — PL2, PL3, PL8, PL10, PD15, PD16, PD18, PD21 — is plain GPIO with no fixed role.

Device nodes assume the stock overlays are enabled. If a bus is disabled in armbian-config the pins revert to GPIO and the node disappears.

Two numbering schemes

the big trap

The same physical pin has two different numbers, and which one is right depends entirely on which tool you are holding.

libgpiod — banks are split across two chips

PA–PH live on gpiochip1 (pio)line = base + index · PA 0, PC 64, PD 96, PH 224 so PH3, header pin 24224 + 3 = gpiochip1 line 227 PL lives on its own chip (r_pio)gpiochip0, line = index so PL10, header pin 15gpiochip0 line 10

wiringOP — one flat space

same formula for A–HPH3 → 227 — agrees with libgpiod but PL is offset by 11 banksPL10 → 352 + 10 = 362 — disagrees

where this bitesCopy a PL pin number out of a gpio readall table into a gpioset command and you will drive a completely different pin, or get an out-of-range error. The PD and PH pins happen to agree, which makes the PL disagreement worse — you will trust the pattern right up until it breaks.

Power pins and budget

what you can draw
Pins 1, 173.3 V out — logic rail, modest current
Pins 2, 45 V out — straight off the USB-C input rail
Pins 6, 9, 14, 20, 25GND — five of them, use the nearest one

Logic is 3.3 V and is not 5 V tolerant. The H6 pads will not survive a 5 V signal driven into them; level-shift anything coming from an Arduino running at 5 V.

shared budgetThe 5 V pins come off the same rail feeding the SoC, USB and Ethernet. A supply that is only just adequate at 3 A will brown out the board when you hang a motor driver or a strip of LEDs off pin 2. Power anything hungry separately and share only ground.

No HAT will fit

mechanical

Twenty-six pins, not forty. A Raspberry Pi HAT will physically overhang, and even where a connector seats, the signals underneath are wrong — the Pi's I2C1 on pins 3/5 happens to line up, but SPI, UART and every GPIO number beyond that does not.

What does work: jumper wires to breadboard, and any I2C or SPI peripheral wired by function rather than by header position.

The header is on the bottom edge of the board rather than the long top edge, which also rules out most Pi-shaped cases and stacking hardware.

04 · GPIO in Practice

Three toolchains, in the order you should reach for them.

libgpiod · the right answer

modern

Character-device GPIO. Present on any current kernel, no board-specific build, and the only interface that will still exist in five years.

installsudo apt install gpiod libgpiod-dev what chips are there?gpiodetect — expect gpiochip0 (r_pio) and gpiochip1 (pio) drive PH3 (pin 24) highgpioset gpiochip1 227=1 read PD21 (pin 22)gpioget gpiochip1 117 drive PL10 (pin 15) — different chipgpioset gpiochip0 10=1 watch an input for edgesgpiomon gpiochip1 114

gpioset releases the line when it exits, so the pin returns to input. To hold a level, keep the process alive — gpioset --mode=wait, or use the library rather than the CLI.

wiringOP

vendor tooling

Orange Pi's fork of WiringPi. Useful mainly for one thing: gpio readall prints a table of the header with live pin modes, which is the fastest way to see what an overlay has claimed.

build itgit clone https://github.com/orangepi-xunlong/wiringOP cd wiringOP && sudo ./build clean && sudo ./build the useful commandgpio readall toggle by wiringOP numbergpio mode 2 out · gpio write 2 1

expect OFFFresh out of the box gpio readall often shows every mode as OFF. That is normal — the pins are unclaimed. Enabling an overlay in armbian-config is what makes modes appear.

Remember the PL offset: wiringOP calls PL10 362, libgpiod calls it gpiochip0 line 10.

sysfs

deprecated

The old /sys/class/gpio interface still works on vendor kernels and is all over the forum posts you will find. It was removed from mainline in 2020 and should be treated as read-only knowledge.

the numbers match libgpiod's global spaceecho 227 > /sys/class/gpio/export echo out > /sys/class/gpio/gpio227/direction echo 1 > /sys/class/gpio/gpio227/value

If a tutorial tells you to export a number and it fails, you are on a kernel that dropped sysfs — translate to gpioset rather than hunting for a fix.

Python

scripting
the maintained bindingsudo apt install python3-libgpiod import gpiod chip = gpiod.Chip("gpiochip1") line = chip.get_line(227)# PH3, header pin 24 line.request(consumer="demo", type=gpiod.LINE_REQ_DIR_OUT) line.set_value(1)

OPi.GPIO exists and mimics RPi.GPIO's API, which makes porting Pi code quick — but it is community-maintained and board tables drift. Check it knows this board before trusting its pin numbers.

Anything written against RPi.GPIO assumes BCM numbering and a 40-pin header. The pin numbers will not transfer; only the structure will.

05 · Buses

One of each, and how to turn them on.

I2C0

pins 3 & 5
pins3 = PD26 SDA · 5 = PD25 SCK enablesudo armbian-config → System → Hardware → i2c0 scansudo apt install i2c-tools && i2cdetect -y 0

Pull-ups are on the board, so a bare sensor usually works without adding your own. If you hang a long cable or many devices off it and see NAKs, that assumption is the first thing to revisit.

The PMIC is not on this bus — it is on R_I2C (PL0/PL1), a separate controller. Nothing you do on i2c-0 can upset it.

SPI1

pins 19–24
pins19 MOSI (PH5) · 21 MISO (PH6) · 23 CLK (PH4) · 24 CS (PH3) enablearmbian-config → Hardware → spi1 node/dev/spidev1.0 loopback test — jumper 19 to 21spidev_test -D /dev/spidev1.0 -v

One chip-select is brought out. For a second device, drive any spare GPIO as CS yourself and keep it out of the overlay's hands.

All four SPI pins are PH bank, so they are all on gpiochip1 at 224 + index — 227 through 230.

UART3

pins 11 & 13
pins11 = PD24 RX · 13 = PD23 TX node/dev/ttyS3 talk to somethingscreen /dev/ttyS3 115200 · or minicom -D /dev/ttyS3

This is not the console. The debug console is the separate 3-pin header — see §08. UART3 is a free port for talking to a microcontroller, a GPS, a modem.

3.3 VCross TX to RX, share ground, and level-shift anything running at 5 V.

PWM0

pin 7

One hardware PWM, on pin 7 (PD22). Enough for a fan, a servo, or a backlight; not enough for anything that needs several synchronised channels.

enable, then find the chipls /sys/class/pwm/ export and configure — 1 kHz, 50 %echo 0 > /sys/class/pwm/pwmchip0/export echo 1000000 > /sys/class/pwm/pwmchip0/pwm0/period ns echo 500000 > /sys/class/pwm/pwmchip0/pwm0/duty_cycle echo 1 > /sys/class/pwm/pwmchip0/pwm0/enable

Period and duty are in nanoseconds. Duty must be ≤ period or the write is rejected with EINVAL.

06 · Getting an OS On It

The board ships with Android on the eMMC. Almost nobody wants that.

Which image

decide first
Armbianthe practical answer. Current kernels, sane defaults, armbian-config, and an actual update path
Orange Pi officialUbuntu/Debian builds from Xunlong. They boot, they have the vendor drivers, and they age fast
Android 9what is on the eMMC out of the box. Useful for a five-minute smoke test, then overwrite it
Generic arm64don't — no Wi-Fi, and no Ethernet before kernel 6.3

bench noteYour own inventory note already says it: run Armbian, not the vendor image. That remains the right call.

Whatever you pick, verify it before writing: sha256sum -c *.sha.

Boot order

BROM

The H6 boot ROM looks for a bootloader in a fixed order:

1SMHC0 — the microSD card 2SMHC2 — the onboard eMMC 3SPI0 — SPI NOR flash (not fitted on this board) 4FEL — USB recovery over the OTG port

this is your safety netA card in the slot always wins. You cannot brick this board by ruining the eMMC — write a good image to microSD, insert, power on, and you are back. That is worth remembering before you experiment.

If a card is present but its bootloader is bad, the BROM can fall through to eMMC and boot that instead, which looks like the card being ignored. Bad image, not bad slot.

microSD → eMMC

the normal install
1 · write the image to a cardbalenaEtcher or dd — nothing board-specific here 2 · boot from the cardfirst boot resizes the filesystem and reboots itself; let it 3 · move it to eMMCsudo armbian-config → System → Install → Boot from eMMC, system on eMMC 4 · power down, remove the card, power upsudo poweroff

You are copying a running system onto the eMMC, so do it before you have built anything on the card that you care about — or accept that whatever exists at that moment is what gets copied.

8 GB fills faster than you expect once a desktop and a kernel or two are installed. Check with df -h before assuming you have room.

FEL mode

last resort

With no bootable card and no bootable eMMC, the BROM falls through to FEL — an Allwinner USB recovery protocol on the OTG port, which on this board is the same USB-C you power it from.

on the hostsudo apt install sunxi-tools is the board there?sunxi-fel version

In practice you will almost never need this, precisely because the microSD path above always works. It matters if you have somehow written a bad bootloader to eMMC and have no card.

FEL is also how the vendor's PhoenixCard/PhoenixSuit tools push Android images.

07 · First Ten Minutes

Headless, no monitor, no keyboard — the way this board is best used.

Headless bring-up

wired
1 · Ethernet in, USB-C inwired first — Wi-Fi depends on a driver that may not be there 2 · find itping orangepi3lts.local or check the router's lease table 3 · sweep if that failsnmap -sn 192.168.1.0/24 · or: arp -a | grep -i xunlong 4 · inssh root@<ip> Armbian's first login forces a password change and makes a user

Wi-Fi first?Don't. If wireless does not come up you cannot tell whether it is the driver, the antenna or the credentials. Get in over the wire, confirm ip link shows a wlan0, then configure it.

Confirm what you got

sanity checks
kernel and boarduname -a · cat /etc/armbian-release all four cores, at speednproc · lscpu | grep MHz memory really 2 GB?free -h — expect ~1.9 Gi total running from eMMC or card?lsblk — mmcblk2 is eMMC, mmcblk0 is the card did Ethernet bind?ethtool eth0 | grep Speed — want 1000Mb/s is wireless present at all?ip link | grep wlan

Device names vary by kernel: eMMC is usually mmcblk2 and the card mmcblk0, but confirm with lsblk rather than assuming before you write to either.

Settle it in

worth doing once
hostnamesudo hostnamectl set-hostname opi3 timezone and localesudo armbian-config → Personal key-only SSHssh-copy-id user@opi3 then disable password auth keep the log spam off the eMMCsudo armbian-config → System → zram / log2ram swap, because 2 GBsudo fallocate -l 2G /swapfile && sudo mkswap /swapfile sudo swapon /swapfile then add it to /etc/fstab

eMMC has finite write cycles and 8 GB of it. Moving logs to RAM is not paranoia on a board that may run for years.

08 · Serial Console

The 3-pin header that shows you what the board is doing before Linux exists.

The debug header

GND · RX · TX

Three pins on the top edge, beside the HDMI connector. This is a console, not a general-purpose port — U-Boot and the kernel both talk on it from the first instant of boot.

OrderGND, RX, TX — in that order along the header
Speed115200 8N1, no flow control
Levels3.3 V logic, 5 V tolerant on the input
wiring a USB-TTL dongleadapter GND → board GND adapter TX → board RX · adapter RX → board TX do NOT connectadapter VCC → anything power the board from USB-C

Set the dongle to 3.3 V if it has a jumper. A 5 V adapter driving the board's RX is the classic way to damage an H6 pad.

Using it

from the Mac
find the adapterls /dev/tty.usb* — CP2102, CH340 and FTDI all work open the consolescreen /dev/tty.usbserial-0001 115200 leave screenCtrl-A then K · or Ctrl-A Ctrl-\ alternativeminicom -D /dev/tty.usbserial-0001 -b 115200

What it is for: a board that will not appear on the network, a kernel panic you cannot read, interrupting U-Boot to change the boot device, or watching exactly where a boot hangs. It is the difference between debugging and guessing.

Garbage on screen at the right baud usually means the adapter is at 5 V, or TX and RX are not crossed.

09 · Power & Heat

Underfeeding this board is the most common self-inflicted fault.

5 V / 3 A, and mean it

USB-C

The board wants 5 V at 3 A over USB-C. Note what that is not: it is a plain 5 V supply on a USB-C connector, not a USB-PD negotiation. A PD-only charger that refuses to output anything until it is asked will leave the board dead.

Symptoms of undervoltrandom reboots under load, Ethernet dropping, USB devices vanishing, eMMC write errors
Cable mattersa thin charging cable drops enough at 2–3 A to cause exactly the above
Phone chargersoften fine at idle, then brown out the moment all four cores spin up

before debugging anything elseIf the board is behaving strangely, swap the supply and the cable first. It is the answer far more often than it deserves to be.

Thermals

A53 × 4 @ 1.8 GHz

The H6 will happily run warm. There is no heatsink fitted from the factory and the SoC sits in the middle of the board with nothing over it.

current temperaturecat /sys/class/thermal/thermal_zone0/temp — millidegrees readable, livewatch -n1 "awk '{print \$1/1000\"°C\"}' /sys/class/thermal/thermal_zone0/temp" what the governor is doingcat /sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq

A small adhesive heatsink is worth the money for any sustained load. Passive is enough — this is not a Pi 5.

The AXP805 gives you a genuine soft power-off. Use poweroff and the button rather than pulling the cable, especially with the root filesystem on eMMC.

10 · Command Index

The commands you will actually type on this board, grouped by what you are trying to find out.

Identify the board

what am I on
cat /etc/armbian-releaseboard name, branch, kernel family
cat /proc/device-tree/model“OrangePi 3 LTS” — straight from the DT
uname -akernel version; decides Ethernet and Wi-Fi support
lscpu4× A53, aarch64, current MHz
free -h~1.9 Gi usable of the 2 GB
lsblkmmcblk2 eMMC · mmcblk0 microSD
df -h /how much of the 8 GB is left

GPIO & buses

pins
gpiodetectlists gpiochip0 (r_pio) and gpiochip1 (pio)
gpioinfo gpiochip1every line, its name and who has claimed it
gpioset gpiochip1 227=1PH3, header pin 24, high
gpioget gpiochip1 117read PD21, header pin 22
gpiomon gpiochip0 10watch PL10, header pin 15, for edges
gpio readallwiringOP's header table with live modes
i2cdetect -y 0scan I2C0 on pins 3 and 5
ls /dev/spidev*expect spidev1.0 when SPI1 is enabled
ls /sys/class/pwm/PWM0 on pin 7

Network & radio

connectivity
ip -br aevery interface and address, one line each
ethtool eth0link speed — confirm 1000Mb/s
lsmod | grep uwethe Wi-Fi question — no uwe5622, no wireless
iw devwireless interfaces the kernel knows about
nmcli device wifi listscan, if NetworkManager is in use
hciconfig -aBluetooth, same module and same driver dependency
dmesg | grep -iE "phy|8531"did the Motorcomm PHY bind?

System & storage

housekeeping
armbian-configoverlays, eMMC install, zram, locales — the main tool
armbianmonitor -mlive temperature, frequency and throttling
armbianmonitor -uuploads a full diagnostic — what to paste in a forum post
cat /sys/class/thermal/thermal_zone0/tempSoC temperature, millidegrees
systemd-analyze blamewhat is slowing boot
journalctl -p err -bthis boot's errors only
poweroffuse it — the AXP805 does a real power-down

11 · Traps

Things that are true, poorly documented, and will each cost you an evening.

The Wi-Fi is not Broadcom

AW859A

The module is a Unisoc UWE5622, not the Ampak AP6256 its predecessor used. There is no mainline driver. A generic arm64 image gives you a board that boots perfectly and has no wireless interface whatsoever.

Check lsmod | grep uwe before suspecting the antenna, the credentials or the router.

Ethernet needs kernel 6.3+

YT8531C

The Motorcomm PHY only got a mainline driver in 6.3. Older generic images will show eth0 down, or no interface at all. Vendor and Armbian images carry the driver regardless of kernel age.

Full mainline device-tree support for this specific board landed in 2025 — anything older than that is vendor-tree territory.

PL pins number differently

gpiochip0

PL2, PL3, PL8 and PL10 are on gpiochip0, not gpiochip1, and their line number is the bare index — PL10 is line 10. wiringOP calls the same pin 362. Every other header pin agrees between the two tools, which is exactly what makes this one bite.

And PL0/PL1 never reach the header at all — the AXP805 has them.

26 pins, not 40

no HATs

No Raspberry Pi HAT fits — not mechanically, and not electrically past the first few pins. Header position differs too: it is on the short bottom edge, so Pi-shaped cases and stacking kits are out.

Wire peripherals by function — SDA to SDA — never by copying a Pi pin number.

USB-C is not USB-PD

power

The connector is Type-C but the board expects a plain 5 V / 3 A. A charger that only speaks PD and waits to be asked may deliver nothing. A thin cable will sag under load and produce reboots that look like software faults.

Swap supply and cable before debugging anything intermittent.

The card always wins

boot order

BROM checks microSD before eMMC, so a good card overrides whatever is on the eMMC. That is your recovery path — and also why a forgotten card in the slot can silently boot a stale system you thought you had replaced.

If a card is in and the board still boots eMMC, the card's bootloader is bad, not ignored.

3.3 V logic, no tolerance

electrical

Header GPIO is 3.3 V and not 5 V tolerant. A 5 V Arduino output wired straight to a pin can damage the pad. Level-shift, or use a divider on inputs at minimum.

The debug UART input is 5 V tolerant; the GPIO header is not. Do not generalise from one to the other.

Fit the antenna

u.FL

The whip clips onto a u.FL socket at the bottom edge and is easy to leave in the box. Without it, wireless works across a desk and nowhere else — which reads exactly like a driver or signal-strength problem.

u.FL connectors are rated for very few mating cycles. Click it on once and leave it.

8 GB goes fast

eMMC

A desktop image plus a couple of kernel updates will fill the eMMC. Watch df -h, keep /var/log in RAM with zram or log2ram, and put anything bulky on USB.

eMMC also has finite write endurance. A chatty daemon logging to disk for a year is a real way to wear it out.

Don't chase H6 PCIe

SoC quirk

The H6's PCIe controller only maps 64 KB of address space at a time, so mainline cannot drive it properly and never will. You will find forum threads and patch sets about it. None of it applies to this board — the 3 LTS exposes no PCIe slot and its USB 3.0 is native.

provenanceBoard specifications, port layout and the 26-pin pinout come from Xunlong's own Orange Pi 3 LTS wiki — the hardware specification table, the top and bottom board photographs, and the official pinout diagram. The pin table was independently cross-checked against wiringOP's physToGpio_3 and ORANGEPI_PIN_MASK_3 arrays, which agree with the vendor diagram pin for pin. Bus device nodes follow the MainsailOS board notes. Silicon details — the H6 PCIe addressing quirk, the AXP805 on R_I2C, the AW859A being a Unisoc UWE5622 rather than an Ampak part, and the YT8531C's mainline driver arriving in kernel 6.3 — come from linux-sunxi, CNX Software, the Motorcomm driver patches and the Linux netdev archives. Everything about probing, level shifting, supply sag and rework practice is general bench knowledge, not vendor documentation.